1. Field
Embodiments of the present invention relate to a NOR-type flash memory device, and more particularly, to a NOR-type flash memory device capable of reducing or eliminating program malfunctions.
2. Discussion of Related Art
A flash memory device having a bulk-erase function may have a stack-type gate structure in which a floating gate and a control gate are stacked. A flash memory device having flash memory cells has widely been used for portable electronic devices (e.g., laptop computers, personal digital assistants (PDAs), or cellular phones), computer basic input/output systems (computer BIOSs), and printers.
In circuital aspects, flash memory devices may be classified into NAND-type flash memory devices and NOR-type flash memory devices. A NOR-type flash memory device is advantageous for high-speed operations because respective flash memory cells are connected in parallel between a cell bit line and a ground voltage.
FIG. 1 is a diagram of a portion of a conventional NOR-type flash memory device, which illustrates a portion of a memory array MARR in which flash memory cells are disposed, and circuits related to the portion of the memory array MARR. Referring to FIG. 1, the memory array MARR includes a plurality of memory sectors MSEC, each of which includes a plurality of flash memory cells MC arranged on a matrix structure including a plurality of word lines WL and a plurality of cell bit lines CBL. In this case, each of the cell bit lines CBL is connected to a sector bit line TBL (e.g., a first sector bit line TBL<1> or a second sector bit line TBL<2>) through a respective connection switch CNSW. Also, the plurality of sector bit lines TBL are connected to a global bit line GBL through respective global switches GLSW. In this case, a program voltage (of about 5V) may be applied from a sector bit line TBL corresponding to the global bit line GBL to a cell bit line CBL connected to a programmed flash memory cell.
In the NOR-type flash memory device of FIG. 1, voltages of the cell bit lines CBL in a case in which a specific flash memory cell MC<1,2> is programmed will now be examined. A program voltage VPRO of about 5V may be applied to a cell bit line CBL<2> connected to the specific flash memory cell MC<1,2> (i.e., the programmed cell bit line CBL<2>).
However, during the application of a program voltage to the programmed cell bit line CBL<2>, as shown in FIG. 2, adjacent cell bit lines CBL<1> and CBL<3> may be put into a floating state. In this case, during the programming of the flash memory cells, the adjacent cell bit lines CBL<1> and CBL<3>, which are to be put into a program inhibition state, may be boosted to a considerably high voltage due to coupling noise between the cell bit lines CBL<1> and CBL<3> and the programmed cell bit line CBL<2>.
Thus, a conventional NOR-type flash memory device may suffer malfunctions caused by unintentionally programming flash memory cells MC<1,1> and MC<1,3> connected to the adjacent cell bit lines CBL<1> and CBL<3>.
For reference, in FIG. 1, connection switches CNSW may be driven to connect respective bit lines CBL to their corresponding sector bit line TBL in response to signals provided by cell column decoders. Also, global switches GLSW may be driven to connect respective sector bit lines TBL to a global bit line GBL in response to signals provided by a global decoder.